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Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_PRELOAD_RST_CTRL

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Interpret as L1_CACHE_PRELOAD_RST_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_PLD_RST)L1_ICACHE0_PLD_RST 0 (L1_ICACHE1_PLD_RST)L1_ICACHE1_PLD_RST 0 (L1_ICACHE2_PLD_RST)L1_ICACHE2_PLD_RST 0 (L1_ICACHE3_PLD_RST)L1_ICACHE3_PLD_RST 0 (L1_CACHE_PLD_RST)L1_CACHE_PLD_RST

Description

Cache Preload Reset control register

Fields

L1_ICACHE0_PLD_RST

set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.
L1_ICACHE1_PLD_RST

set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.
L1_ICACHE2_PLD_RST

Reserved
L1_ICACHE3_PLD_RST

Reserved
L1_CACHE_PLD_RST

set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data